np0.h File Reference

Header file for nPZero Driver. More...

Go to the source code of this file.

Data Structures
struct	np0_register_sleep_rst_s
struct	np0_register_id_s
struct	np0_register_sta1_s
struct	np0_register_sta2_s
struct	np0_register_pswctl_s
struct	np0_register_syscfg1_s
struct	np0_register_syscfg2_s
struct	np0_register_syscfg3_s
struct	np0_register_tout_s
struct	np0_register_intcfg_s
struct	np0_register_cfgp_s
struct	np0_register_modp_s
struct	np0_register_perp_s
struct	np0_register_ncmdp_s
struct	np0_register_addrp_s
struct	np0_register_rregp_s
struct	np0_register_throvp_s
struct	np0_register_thrunp_s
struct	np0_register_twtp_s
struct	np0_register_tcfgp_s
struct	np0_register_throva1_s
struct	np0_register_throva2_s
struct	np0_register_thruna1_s
struct	np0_register_thruna2_s
struct	np0_register_valp_s
struct	np0_register_adc_core_s
struct	np0_register_adc_ext_s
struct	np0_register_sram_s
struct	np0_status_s
struct	np0_adc_config_channels_s
struct	np0_peripheral_config_s
struct	np0_device_config_s

Enumerations
enum	np0_resetsource_e { RESETSOURCE_NONE = 0x00 , RESETSOURCE_PWR_RESET = 0x01 , RESETSOURCE_EXT_RESET = 0x02 , RESETSOURCE_SOFT_RESET = 0x04 }
enum	np0_host_power_mode_e { HOST_POWER_MODE_SWITCH = 0x01 , HOST_POWER_MODE_LOGIC_OUTPUT = 0x02 , HOST_POWER_MODE_LOGIC_OUTPUT_INV = 0x03 }
enum	np0_psw_e { PSW_LP1 = 0x01 , PSW_LP2 = 0x02 , PSW_LP3 = 0x03 , PSW_LP4 = 0x04 }
enum	np0_power_mode_e { POWER_MODE_DISABLED = 0x00 , POWER_MODE_PERIODIC = 0x01 , POWER_MODE_ALWAYS_ON = 0x03 }
enum	np0_polling_mode_e { POLLING_MODE_PERIODIC_READ_COMPARE_THRESHOLD = 0x00 , POLLING_MODE_PERIODIC_WAIT_INTERRUPT_COMPARE_THRESHOLD , POLLING_MODE_PERIODIC_WAIT_INTERRUPT = 0x02 , POLLING_MODE_ASYNC_WAIT_INTERRUPT = 0x03 }
enum	np0_power_switch_mode_e { POWER_SWITCH_MODE_VOLTAGE_DETECTION = 0x00 , POWER_SWITCH_MODE_STANDARD = 0x01 , POWER_SWITCH_MODE_LOGIC_OUTPUT_HIGH = 0x02 , POWER_SWITCH_MODE_LOGIC_OUTPUT_LOW = 0x03 }
enum	np0_interrupt_pin_mode_e { INTERRUPT_PIN_MODE_INPUT_ACTIVE_HIGH = 0x00 , INTERRUPT_PIN_MODE_INPUT_ACTIVE_LOW = 0x01 , INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_HIGH = 0x02 , INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_LOW = 0x03 }
enum	np0_comparison_mode_e { COMPARISON_MODE_INSIDE_THRESHOLD = 0x00 , COMPARISON_MODE_OUTSIDE_THRESHOLD = 0x01 }
enum	np0_data_type_e { DATA_TYPE_UINT16 = 0x00 , DATA_TYPE_INT16 = 0x01 , DATA_TYPE_UINT8 = 0x02 }
enum	np0_spimod_e { SPIMOD_SPI_MODE_0 = 0x00 , SPIMOD_SPI_MODE_1 = 0x01 , SPIMOD_SPI_MODE_2 = 0x02 , SPIMOD_SPI_MODE_3 = 0x03 }
enum	np0_sclk_sel_e { SYS_CLOCK_10HZ = 0x00 , SYS_CLOCK_32KHZ = 0x01 }
enum	np0_sclk_div_e {   SCLK_DIV_DISABLE = 0x00 , SCLK_DIV_2 = 0x01 , SCLK_DIV_4 = 0x03 , SCLK_DIV_8 = 0x05 ,   SCLK_DIV_16 = 0x07 }
enum	np0_adc_clk_e { ADC_CLK_SC = 0x00 , ADC_CLK_64 = 0x01 , ADC_CLK_256 = 0x02 , ADC_CLK_1024 = 0x03 }
enum	np0_io_str_e { IO_STR_NORMAL = 0x00 , IO_STR_HIGH = 0x01 }
enum	np0_i2c_pull_sel_e { I2C_PULL_DISABLE = 0x00 , I2C_PULL_ALWAYS_ON = 0x01 , I2C_PULL_AUTO = 0x03 }
enum	np0_spi_auto_e { SPI_PINS_ALWAYS_ON = 0x00 , SPI_PINS_AUTO_DISABLE = 0x01 }
enum	np0_xo_clkout_div_e {   XO_CLK_OFF = 0x00 , XO_CLK_32K = 0x01 , XO_CLK_16K = 0x02 , XO_CLK_8K = 0x03 ,   XO_CLK_4K = 0x04 , XO_CLK_2K = 0x05 , XO_CLK_1K = 0x06 }
enum	np0_states_e { DISABLED = 0x00 , ENABLED = 0x01 }
enum	np0_multibyte_e { MULTIBYTE_TRANSFER_DISABLE = 0x00 , MULTIBYTE_TRANSFER_ENABLE = 0x01 }
enum	np0_com_protocol_e { COM_I2C = 0x00 , COM_SPI = 0x01 }
enum	np0_endianess_e { ENDIAN_LITTLE = 0x00 , ENDIAN_BIG = 0x01 }
enum	np0_int_pin_pull_e { INT_PIN_PULL_DISABLED = 0x00 , INT_PIN_PULL_LOW = 0x01 , INT_PIN_PULL_HIGH = 0x03 }
enum	np0_pre_wait_time_e { PRE_WAIT_TIME_DISABLED = 0x00 , PRE_WAIT_TIME_EXTEND_256 = 0x01 , PRE_WAIT_TIME_EXTEND_4096 = 0x03 }
enum	np0_post_wait_time_e { POST_WAIT_TIME_DISABLED = 0x00 , POST_WAIT_TIME_EXTEND_256 = 0x01 , POST_WAIT_TIME_EXTEND_4096 = 0x03 }
enum	np0_wakeup_e { WAKEUP_ANY = 0x00 , WAKEUP_ALL = 0x01 }

Functions
np0_status_e	np0_write_SLEEP_RST (uint8_t sleep_rst_value)
	Writes the sleep_rst struct to the sleep_rst register.
np0_status_e	np0_read_SLEEP_RST (uint8_t *sleep_rst_value)
	Reads the sleep_rst register and stores it in np0_register_sleep_rst_s struct.
np0_status_e	np0_read_ID (uint8_t *id)
	Reads the ID register and stores it in np0_register_id_s struct.
np0_status_e	np0_read_STA1 (np0_register_sta1_s *sta1)
	Reads the sta1 register and writes it to np0_register_sta1_s struct.
np0_status_e	np0_read_STA2 (np0_register_sta2_s *sta2)
	Reads the sta2 register and writes it to np0_register_sta2_s struct.
np0_status_e	np0_write_PSWCTL (const np0_register_pswctl_s pswctl)
	Writes the pswctl struct to the pswctl register.
np0_status_e	np0_read_PSWCTL (np0_register_pswctl_s *pswctl)
	Reads the pswctl register and writes it to np0_register_pswctl_s struct.
np0_status_e	np0_write_SYSCFG1 (const np0_register_syscfg1_s syscfg1)
	Writes the syscfg1 struct to the syscfg1 register.
np0_status_e	np0_read_SYSCFG1 (np0_register_syscfg1_s *syscfg1)
	Reads the syscfg1 register and writes it to np0_register_syscfg1_s struct.
np0_status_e	np0_write_SYSCFG2 (const np0_register_syscfg2_s syscfg2)
	Writes the syscfg2 struct to the syscfg2 register.
np0_status_e	np0_read_SYSCFG2 (np0_register_syscfg2_s *syscfg2)
	Reads the syscfg2 register and writes it to np0_register_syscfg2_s struct.
np0_status_e	np0_write_SYSCFG3 (const np0_register_syscfg3_s syscfg3)
	Writes the syscfg3 struct to the syscfg2 register.
np0_status_e	np0_read_SYSCFG3 (np0_register_syscfg3_s *syscfg3)
	Reads the syscfg3 register and writes it to np0_register_syscfg2_s struct.
np0_status_e	np0_write_TOUT (const np0_register_tout_s tout)
	Writes the tout struct to the TOUT_L and TOUT_H registers.
np0_status_e	np0_read_TOUT (np0_register_tout_s *tout)
	Reads the tout register and writes it to np0_register_tout_s struct.
np0_status_e	np0_write_INTCFG (const np0_register_intcfg_s intcfg)
	Writes the intcfg struct to the intcfg register.
np0_status_e	np0_read_INTCFG (np0_register_intcfg_s *intcfg)
	Reads the intcfg register and writes it to np0_register_intcfg_s struct.
np0_status_e	np0_write_THROVA1 (const np0_register_throva1_s throva1)
	Writes the throva1 struct to the throva1 register.
np0_status_e	np0_read_THROVA1 (np0_register_throva1_s *throva1)
	Reads the throva1 register and writes it to np0_register_throva1_s struct.
np0_status_e	np0_write_THROVA2 (const np0_register_throva2_s throva2)
	Writes the throva2 struct to the throva2 register.
np0_status_e	np0_read_THROVA2 (np0_register_throva2_s *throva2)
	Reads the throva2 register and writes it to np0_register_throva2_s struct.
np0_status_e	np0_write_THRUNA1 (const np0_register_thruna1_s thruna1)
	Writes the thruna1 struct to the TRHUNA1 register.
np0_status_e	np0_read_THRUNA1 (np0_register_thruna1_s *thruna1)
	Reads the thruna1 register and writes it to np0_register_thruna1_s struct.
np0_status_e	np0_write_THRUNA2 (const np0_register_thruna2_s thruna2)
	Writes the thruna2 struct to the TRHUNA2 register.
np0_status_e	np0_read_THRUNA2 (np0_register_thruna2_s *thruna2)
	Reads the thruna2 register and writes it to np0_register_thruna2_s struct.
np0_status_e	np0_read_ADC_CORE (np0_register_adc_core_s *adc_core)
	Reads the last value from internal ADC channel (VBAT) and stores it in np0_register_adc_core_s struct.
np0_status_e	np0_read_ADC_EXT (np0_register_adc_ext_s *adc_ext)
	Reads the last value from external ADC channel (ADC_IN) and stores it in np0_register_adc_ext_s struct.
np0_status_e	np0_write_SRAM (const uint8_t sram_reg, const uint8_t sram)
	Write one byte to one register in SRAM.
np0_status_e	np0_read_SRAM (const uint8_t sram_reg, np0_register_sram_s *sram)
	Reads one SRAM register and writes it to np0_register_sram_s struct.
np0_status_e	np0_write_CFGP (const np0_psw_e sw, const np0_register_cfgp_s cfgp)
	Writes the cfgp struct to the cfgp register that is connected to the low power switch.
np0_status_e	np0_read_CFGP (const np0_psw_e sw, np0_register_cfgp_s *cfgp)
	Reads the cfgp register that is connected to the low power switch and writes it to np0_register_cfgp_s struct.
np0_status_e	np0_write_MODP (const np0_psw_e sw, const np0_register_modp_s modp)
	Writes the modp struct to the modp register that is connected to the low power switch.
np0_status_e	np0_read_MODP (const np0_psw_e sw, np0_register_modp_s *modp)
	Reads the modp register that is connected to the low power switch and writes it to np0_register_modp_s struct.
np0_status_e	np0_write_PERP (const np0_psw_e sw, const np0_register_perp_s perp)
	Writes the perp struct to the perp register that is connected to the low power switch.
np0_status_e	np0_read_PERP (const np0_psw_e sw, np0_register_perp_s *perp)
	Reads the perp register that is connected to the low power switch and writes it to np0_register_perp_s struct.
np0_status_e	np0_write_NCMDP (const np0_psw_e sw, const np0_register_ncmdp_s ncmdp)
	Writes the ncmdp struct to the ncmdp register that is connected to the low power switch.
np0_status_e	np0_read_NCMDP (const np0_psw_e sw, np0_register_ncmdp_s *ncmdp)
	Reads the ncmdp register that is connected to the low power switch and writes it to np0_register_ncmdp_s struct.
np0_status_e	np0_write_ADDRP (const np0_psw_e sw, const np0_register_addrp_s addrp)
	Writes the addrp struct to the addrp register that is connected to the low power switch.
np0_status_e	np0_read_ADDRP (const np0_psw_e sw, np0_register_addrp_s *addrp)
	Reads the addrp register that is connected to the low power switch and writes it to np0_register_addrp_s struct.
np0_status_e	np0_write_RREGP (const np0_psw_e sw, const np0_register_rregp_s rregp)
	Writes the rregp struct to the rregp register that is connected to the low power switch.
np0_status_e	np0_read_RREGP (const np0_psw_e sw, np0_register_rregp_s *rregp)
	Reads the rrep register that is connected to the low power switch and writes it to np0_register_rregp_s struct.
np0_status_e	np0_write_THROVP (const np0_psw_e sw, const np0_register_throvp_s throvp)
	Writes the throvp struct to the throvp register that is connected to the low power switch.
np0_status_e	np0_read_THROVP (const np0_psw_e sw, np0_register_throvp_s *throvp)
	Reads the throvp register that is connected to the low power switch and writes it to np0_register_throvp_s struct.
np0_status_e	np0_write_THRUNP (const np0_psw_e sw, const np0_register_thrunp_s thrunp)
	Writes the thrunp struct to the thrunp register that is connected to the low power switch.
np0_status_e	np0_read_THRUNP (const np0_psw_e sw, np0_register_thrunp_s *thrunp)
	Reads the thrunp register that is connected to the low power switch and writes it to np0_register_thrunp_s struct.
np0_status_e	np0_write_TWTP (const np0_psw_e sw, const np0_register_twtp_s twtp)
	Writes the twtp struct to the twtp register that is connected to the low power switch.
np0_status_e	np0_read_TWTP (const np0_psw_e sw, np0_register_twtp_s *twtp)
	Reads the twtp register that is connected to the low power switch and writes it to np0_register_twtp_s struct.
np0_status_e	np0_write_TCFGP (const np0_psw_e sw, const np0_register_tcfgp_s tcfgp)
	Writes the tcfgp struct to the tcfgp register that is connected to the low power switch.
np0_status_e	np0_read_TCFGP (const np0_psw_e sw, np0_register_tcfgp_s *tcfgp)
	Reads the tcfgp register that is connected to the low power switch and writes it to np0_register_tcfgp_s struct.
np0_status_e	np0_read_VALP (const np0_psw_e sw, np0_register_valp_s *valp)
	Reads the valp register that is connected to the low power switch and writes it to np0_register_valp_s struct.
np0_status_e	np0_read_register (uint8_t register_address, void *buffer, size_t size)
	Generic function to read from a device register using I2C.

Detailed Description

Header file for nPZero Driver.

This header file contains declarations and definitions for the IPMIC driver for controlling and managing the Intelligent Power Management Integrated Circuit (IPMIC). It provides function prototypes, constants, enumerations and structures necessary for interacting with the IPMIC on register level.

This driver is designed to work with the nPZero IPMIC from Nanopower Semiconductor. It uitilizes I2C communication protocol for interfacing with host MCU.

Enumeration Type Documentation

np0_adc_clk_e

enum np0_adc_clk_e

Controls ADC clock select

Enumerator
ADC_CLK_SC	System clock.
ADC_CLK_64	XO clock divided by 512 (64 Hz).
ADC_CLK_256	XO clock divided by 128 (256 Hz).
ADC_CLK_1024	XO clock divided by 32 (1024 Hz).

np0_com_protocol_e

enum np0_com_protocol_e

Enumerator
COM_I2C	Use I2C as communication protocol.
COM_SPI	Use SPI as communication protocol.

np0_comparison_mode_e

enum np0_comparison_mode_e

Comparison mode for threshold values.

Enumerator
COMPARISON_MODE_INSIDE_THRESHOLD	Compare inside threshold values.
COMPARISON_MODE_OUTSIDE_THRESHOLD	Compare outside threshold values.

np0_data_type_e

enum np0_data_type_e

Data type value of value to be read from peripheral, see np0_register_modp_s.

Enumerator
DATA_TYPE_UINT16	16-bit unsigned integer.
DATA_TYPE_INT16	16-bit signed integer.
DATA_TYPE_UINT8	8-bit unsigned integer.

np0_endianess_e

enum np0_endianess_e

Enumerator
ENDIAN_LITTLE	Little endian.
ENDIAN_BIG	Big endian.

np0_host_power_mode_e

enum np0_host_power_mode_e

Host power switch mode (SW_HP pin), see np0_register_pswctl_s.

Enumerator
HOST_POWER_MODE_SWITCH	Power switch (outputs VBAT or open).
HOST_POWER_MODE_LOGIC_OUTPUT	Logic output (High when host enabled).
HOST_POWER_MODE_LOGIC_OUTPUT_INV	Logic output inverted (Low when host enabled).

np0_i2c_pull_sel_e

enum np0_i2c_pull_sel_e

Controls I2C pull-ups

Enumerator
I2C_PULL_DISABLE	I2C pull-ups disabled
I2C_PULL_ALWAYS_ON	I2C pull-ups always enabled
I2C_PULL_AUTO	I2C pull-ups disabled in sleep

np0_int_pin_pull_e

enum np0_int_pin_pull_e

Enumerator
INT_PIN_PULL_DISABLED
INT_PIN_PULL_LOW
INT_PIN_PULL_HIGH

np0_interrupt_pin_mode_e

enum np0_interrupt_pin_mode_e

Peripheral interrupt pin mode (pins INT*), see np0_register_cfgp_s.

Enumerator
INTERRUPT_PIN_MODE_INPUT_ACTIVE_HIGH	Interrupt input mode (active High).
INTERRUPT_PIN_MODE_INPUT_ACTIVE_LOW	Interrupt input mode (active Low).
INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_HIGH	Peripheral trigger output mode (active High).
INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_LOW	Peripheral trigger output mode (active Low).

np0_io_str_e

enum np0_io_str_e

Controls IO pull-up strength

Enumerator
IO_STR_NORMAL	Normal pull-up strength
IO_STR_HIGH	High pull-up strength

np0_multibyte_e

enum np0_multibyte_e

Enumerator
MULTIBYTE_TRANSFER_DISABLE	Disabled multi-byte transfer.
MULTIBYTE_TRANSFER_ENABLE	Enable multi-byte transfer.

np0_polling_mode_e

enum np0_polling_mode_e

Peripheral polling mode, see np0_register_cfgp_s.

Enumerator
POLLING_MODE_PERIODIC_READ_COMPARE_THRESHOLD	Periodic initialization, read data, compare against threshold.
POLLING_MODE_PERIODIC_WAIT_INTERRUPT_COMPARE_THRESHOLD	Periodic initialization, wait for interrupt, read data, compare against threshold.
POLLING_MODE_PERIODIC_WAIT_INTERRUPT	Periodic initialization, wait for interrupt.
POLLING_MODE_ASYNC_WAIT_INTERRUPT	Wait for asynchronous interrupt.

np0_post_wait_time_e

enum np0_post_wait_time_e

Enumerator
POST_WAIT_TIME_DISABLED	Post-init wait time disable.
POST_WAIT_TIME_EXTEND_256	Post-init wait time x256 clocks.
POST_WAIT_TIME_EXTEND_4096	Post-init wait time x4096 clocks.

np0_power_mode_e

enum np0_power_mode_e

Peripheral power mode, see np0_register_cfgp_s.

Enumerator
POWER_MODE_DISABLED	Disabled.
POWER_MODE_PERIODIC	Periodic power-on.
POWER_MODE_ALWAYS_ON	Always on.

np0_power_switch_mode_e

enum np0_power_switch_mode_e

Peripheral power switch mode (pins SW_LP*), see np0_register_cfgp_s.

Enumerator
POWER_SWITCH_MODE_VOLTAGE_DETECTION	Power switch with output voltage rise detection.
POWER_SWITCH_MODE_STANDARD	Standard power switch mode.
POWER_SWITCH_MODE_LOGIC_OUTPUT_HIGH	Logic output mode (High when peripheral enabled).
POWER_SWITCH_MODE_LOGIC_OUTPUT_LOW	Logic output inverted mode (Low when peripheral enabled).

np0_pre_wait_time_e

enum np0_pre_wait_time_e

Enumerator
PRE_WAIT_TIME_DISABLED	Pre-init wait time disable.
PRE_WAIT_TIME_EXTEND_256	Pre-init wait time x256 clocks.
PRE_WAIT_TIME_EXTEND_4096	Pre-init wait time x4096 clocks.

np0_psw_e

enum np0_psw_e

Low Power switches, see np0_register_pswctl_s.

Enumerator
PSW_LP1	Low power switch 1, Default SPI.
PSW_LP2	Low power switch 2, Default I2C.
PSW_LP3	Low power switch 3, Default SPI.
PSW_LP4	Low power switch 4, Default I2C.

np0_resetsource_e

enum np0_resetsource_e

Enumerations. Reset Reason, see np0_register_sta1_s.

Enumerator
RESETSOURCE_NONE	None.
RESETSOURCE_PWR_RESET	Power-on reset occurred.
RESETSOURCE_EXT_RESET	External reset occurred (via RST pin).
RESETSOURCE_SOFT_RESET	Soft reset occurred (via I2C command).

np0_sclk_div_e

enum np0_sclk_div_e

Controls system clock divider.

Enumerator
SCLK_DIV_DISABLE	Disable clock division.
SCLK_DIV_2	Divided by 2.
SCLK_DIV_4	Divided by 4.
SCLK_DIV_8	Divided by 8.
SCLK_DIV_16	Divided by 16.

np0_sclk_sel_e

enum np0_sclk_sel_e

Controls system clock source between internal slow oscillator or crystal oscillator. (0: Slow oscillator, 1: Crystal oscillator).

Enumerator
SYS_CLOCK_10HZ	10 Hz.
SYS_CLOCK_32KHZ	32.578 kHz.

np0_spi_auto_e

enum np0_spi_auto_e

Controls the SPI pin mode

Enumerator
SPI_PINS_ALWAYS_ON	SPI pins always enabled
SPI_PINS_AUTO_DISABLE	SPI pins disabled in sleep (hi-Z)

np0_spimod_e

enum np0_spimod_e

SPI modes available if SPI is enabled, see np0_register_modp_s.

Enumerator
SPIMOD_SPI_MODE_0	CPOL = 0 CPHA = 0.
SPIMOD_SPI_MODE_1	CPOL = 0 CPHA = 1.
SPIMOD_SPI_MODE_2	CPOL = 1 CPHA = 0.
SPIMOD_SPI_MODE_3	CPOL = 1 CPHA = 1.

np0_states_e

enum np0_states_e

Enumerator
DISABLED	Disabled.
ENABLED	Enabled.

np0_wakeup_e

enum np0_wakeup_e

Enumerator
WAKEUP_ANY
WAKEUP_ALL	Wake up system on any trigger.

np0_xo_clkout_div_e

enum np0_xo_clkout_div_e

Controls CLK_OUT DIV clock select

Enumerator
XO_CLK_OFF	Turned_off.
XO_CLK_32K	Divide by 1 (32 kHz).
XO_CLK_16K	Divide by 2 (16 kHz).
XO_CLK_8K	Divide by 4 (8 kHz).
XO_CLK_4K	Divide by 8 (4 kHz).
XO_CLK_2K	Divide by 16 (2 kHz).
XO_CLK_1K	Divide by 32 (1 kHz).

Function Documentation

np0_read_ADC_CORE()

np0_status_e np0_read_ADC_CORE

(

np0_register_adc_core_s *

adc_core

)

Reads the last value from internal ADC channel (VBAT) and stores it in np0_register_adc_core_s struct.

Parameters

[out]

adc_core

Pointer to ADC Core register where value will be stored.

Returns

np0_status_e Status

np0_read_ADC_EXT()

np0_status_e np0_read_ADC_EXT

(

np0_register_adc_ext_s *

adc_ext

)

Reads the last value from external ADC channel (ADC_IN) and stores it in np0_register_adc_ext_s struct.

Parameters

[out]

adc_ext

Pointer to ADC External register where value will be stored.

Returns

np0_status_e Status

np0_read_ADDRP()

np0_status_e np0_read_ADDRP	(	const np0_psw_e	sw,
		np0_register_addrp_s *	addrp )

Reads the addrp register that is connected to the low power switch and writes it to np0_register_addrp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	addrp	Pointer to Address Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_CFGP()

np0_status_e np0_read_CFGP	(	const np0_psw_e	sw,
		np0_register_cfgp_s *	cfgp )

Reads the cfgp register that is connected to the low power switch and writes it to np0_register_cfgp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	cfgp	Pointer to Config Peripheral where value will be stored.

Returns

np0_status_e Status

np0_read_ID()

np0_status_e np0_read_ID

(

uint8_t *

id

)

Reads the ID register and stores it in np0_register_id_s struct.

Parameters

[out]

id

Pointer to id where value will be stored.

Returns

np0_status_e Status

np0_read_INTCFG()

np0_status_e np0_read_INTCFG

(

np0_register_intcfg_s *

intcfg

)

Reads the intcfg register and writes it to np0_register_intcfg_s struct.

Parameters

[out]

intcfg

Pointer to Interrupt pin config register where value will be stored.

Returns

np0_status_e Status

np0_read_MODP()

np0_status_e np0_read_MODP	(	const np0_psw_e	sw,
		np0_register_modp_s *	modp )

Reads the modp register that is connected to the low power switch and writes it to np0_register_modp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	modp	Pointer to Mode Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_NCMDP()

np0_status_e np0_read_NCMDP	(	const np0_psw_e	sw,
		np0_register_ncmdp_s *	ncmdp )

Reads the ncmdp register that is connected to the low power switch and writes it to np0_register_ncmdp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	ncmdp	Pointer to Number Of Commands register where value will be stored.

Returns

np0_status_e Status

np0_read_PERP()

np0_status_e np0_read_PERP	(	const np0_psw_e	sw,
		np0_register_perp_s *	perp )

Reads the perp register that is connected to the low power switch and writes it to np0_register_perp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	perp	Pointer to Polling Period register where value will be stored.

Returns

np0_status_e Status

np0_read_PSWCTL()

np0_status_e np0_read_PSWCTL

(

np0_register_pswctl_s *

pswctl

)

Reads the pswctl register and writes it to np0_register_pswctl_s struct.

Parameters

[out]

pswctl

Pointer to power switch register where value will be stored.

Returns

np0_status_e Status

np0_read_register()

np0_status_e np0_read_register	(	uint8_t	register_address,
		void *	buffer,
		size_t	size )

Generic function to read from a device register using I2C.

Parameters

register_address	The address of the register to read from.
buffer	Pointer to the buffer where the read data will be stored.
size	The size of the data to read.

Returns

OK if the read operation is successful, ERR otherwise.

np0_read_RREGP()

np0_status_e np0_read_RREGP	(	const np0_psw_e	sw,
		np0_register_rregp_s *	rregp )

Reads the rrep register that is connected to the low power switch and writes it to np0_register_rregp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	rregp	Pointer to Read Register Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_SLEEP_RST()

np0_status_e np0_read_SLEEP_RST

(

uint8_t *

sleep_rst_value

)

Reads the sleep_rst register and stores it in np0_register_sleep_rst_s struct.

Parameters

[out]

sleep_rst_value

Pointer to store the read sleep value.

Returns

np0_status_e Status

np0_read_SRAM()

np0_status_e np0_read_SRAM	(	const uint8_t	sram_reg,
		np0_register_sram_s *	sram )

Reads one SRAM register and writes it to np0_register_sram_s struct.

Parameters

[in]	sram_reg	Register address in SRAM to read a byte from.
[out]	sram	Pointer to SRAM register where value will be stored.

Returns

np0_status_e Status

np0_read_STA1()

np0_status_e np0_read_STA1

(

np0_register_sta1_s *

sta1

)

Reads the sta1 register and writes it to np0_register_sta1_s struct.

Parameters

[out]

sta1

Pointer to status 1 register where value will be stored.

Returns

np0_status_e Status

np0_read_STA2()

np0_status_e np0_read_STA2

(

np0_register_sta2_s *

sta2

)

Reads the sta2 register and writes it to np0_register_sta2_s struct.

Parameters

[out]

sta2

Pointer to status 2 register where value will be stored.

Returns

np0_status_e Status

np0_read_SYSCFG1()

np0_status_e np0_read_SYSCFG1

(

np0_register_syscfg1_s *

syscfg1

)

Reads the syscfg1 register and writes it to np0_register_syscfg1_s struct.

Parameters

[out]

syscfg1

Pointer to system config 1 where value will be stored.

Returns

np0_status_e Status

np0_read_SYSCFG2()

np0_status_e np0_read_SYSCFG2

(

np0_register_syscfg2_s *

syscfg2

)

Reads the syscfg2 register and writes it to np0_register_syscfg2_s struct.

Parameters

[out]

syscfg2

Pointer to System config 2 register where value will be stored..

Returns

np0_status_e Status

np0_read_SYSCFG3()

np0_status_e np0_read_SYSCFG3

(

np0_register_syscfg3_s *

syscfg3

)

Reads the syscfg3 register and writes it to np0_register_syscfg2_s struct.

Parameters

[out]

syscfg3

Pointer to System config 3 register where value will be stored..

Returns

np0_status_e Status

np0_read_TCFGP()

np0_status_e np0_read_TCFGP	(	const np0_psw_e	sw,
		np0_register_tcfgp_s *	tcfgp )

Reads the tcfgp register that is connected to the low power switch and writes it to np0_register_tcfgp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	tcfgp	Pointer to Time To Wait Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_THROVA1()

np0_status_e np0_read_THROVA1

(

np0_register_throva1_s *

throva1

)

Reads the throva1 register and writes it to np0_register_throva1_s struct.

Parameters

[out]

throva1

Pointer to Threshold Over ADC 1 register where value will be stored.

Returns

np0_status_e Status

np0_read_THROVA2()

np0_status_e np0_read_THROVA2

(

np0_register_throva2_s *

throva2

)

Reads the throva2 register and writes it to np0_register_throva2_s struct.

Parameters

[out]

throva2

Pointer to Thershold Over ADC 2 register where value will be stored.

Returns

np0_status_e Status

np0_read_THROVP()

np0_status_e np0_read_THROVP	(	const np0_psw_e	sw,
		np0_register_throvp_s *	throvp )

Reads the throvp register that is connected to the low power switch and writes it to np0_register_throvp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	throvp	Pointer to Threshold Over Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_THRUNA1()

np0_status_e np0_read_THRUNA1

(

np0_register_thruna1_s *

thruna1

)

Reads the thruna1 register and writes it to np0_register_thruna1_s struct.

Parameters

[out]

thruna1

Pointer to Threshold Under ADC 1 register where value will be stored.

Returns

np0_status_e Status

np0_read_THRUNA2()

np0_status_e np0_read_THRUNA2

(

np0_register_thruna2_s *

thruna2

)

Reads the thruna2 register and writes it to np0_register_thruna2_s struct.

Parameters

[out]

thruna2

Pointer to Threshold Under ADC 2 register where value will be stored.

Returns

np0_status_e Status

np0_read_THRUNP()

np0_status_e np0_read_THRUNP	(	const np0_psw_e	sw,
		np0_register_thrunp_s *	thrunp )

Reads the thrunp register that is connected to the low power switch and writes it to np0_register_thrunp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	thrunp	Pointer to Threshold Under Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_TOUT()

np0_status_e np0_read_TOUT

(

np0_register_tout_s *

tout

)

Reads the tout register and writes it to np0_register_tout_s struct.

Parameters

[out]

tout

Pointer to Global Timeout register where value will be stored.

Returns

np0_status_e Status

np0_read_TWTP()

np0_status_e np0_read_TWTP	(	const np0_psw_e	sw,
		np0_register_twtp_s *	twtp )

Reads the twtp register that is connected to the low power switch and writes it to np0_register_twtp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	twtp	Pointer to Time To Wait Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_read_VALP()

np0_status_e np0_read_VALP	(	const np0_psw_e	sw,
		np0_register_valp_s *	valp )

Reads the valp register that is connected to the low power switch and writes it to np0_register_valp_s struct.

Parameters

[in]	sw	Low power switch indicates which peripheral will be read.
[out]	valp	Pointer to Value Peripheral register where value will be stored.

Returns

np0_status_e Status

np0_write_ADDRP()

np0_status_e np0_write_ADDRP	(	const np0_psw_e	sw,
		const np0_register_addrp_s	addrp )

Writes the addrp struct to the addrp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	addrp	Address Peripheral register that holds the value to be written.

Returns

np0_status_e Status

np0_write_CFGP()

np0_status_e np0_write_CFGP	(	const np0_psw_e	sw,
		const np0_register_cfgp_s	cfgp )

Writes the cfgp struct to the cfgp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	cfgp	Config Peripheral register that holds value to be written.

Returns

np0_status_e Status

np0_write_INTCFG()

np0_status_e np0_write_INTCFG

(

const np0_register_intcfg_s

intcfg

)

Writes the intcfg struct to the intcfg register.

Parameters

[in]

intcfg

Interrupt pin config register that holds value to be written.

Returns

np0_status_e Status

np0_write_MODP()

np0_status_e np0_write_MODP	(	const np0_psw_e	sw,
		const np0_register_modp_s	modp )

Writes the modp struct to the modp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	modp	Mode Peripheral register that holds value to be written.

Returns

np0_status_e Status

np0_write_NCMDP()

np0_status_e np0_write_NCMDP	(	const np0_psw_e	sw,
		const np0_register_ncmdp_s	ncmdp )

Writes the ncmdp struct to the ncmdp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	ncmdp	Number Of Commands register that holds the value to be written.

Returns

np0_status_e Status

np0_write_PERP()

np0_status_e np0_write_PERP	(	const np0_psw_e	sw,
		const np0_register_perp_s	perp )

Writes the perp struct to the perp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	perp	Polling Period register that holds the value to be written.

Returns

np0_status_e Status

np0_write_PSWCTL()

np0_status_e np0_write_PSWCTL

(

const np0_register_pswctl_s

pswctl

)

Writes the pswctl struct to the pswctl register.

Parameters

[in]

pswctl

Power switch control register that holds value to be written.

Returns

np0_status_e Status

np0_write_RREGP()

np0_status_e np0_write_RREGP	(	const np0_psw_e	sw,
		const np0_register_rregp_s	rregp )

Writes the rregp struct to the rregp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	rregp	Read Register Peripheral register that holds the value to be written.

Returns

np0_status_e Status

np0_write_SLEEP_RST()

np0_status_e np0_write_SLEEP_RST

(

uint8_t

sleep_rst_value

)

Writes the sleep_rst struct to the sleep_rst register.

When set to OxFF, the device will enter sleep mode, shutting down the host power and assuming control of the I2C bus.

When set to 0xA5, the device will soft reset.

Parameters

[in]

sleep_rst_value

that holds value to be written.

Returns

np0_status_e Status

np0_write_SRAM()

np0_status_e np0_write_SRAM	(	const uint8_t	sram_reg,
		const uint8_t	sram )

Write one byte to one register in SRAM.

Parameters

[in]	sram_reg	Register address in SRAM to write to.
[in]	sram	SRAM register that holds value to be written.

Returns

np0_status_e Status

np0_write_SYSCFG1()

np0_status_e np0_write_SYSCFG1

(

const np0_register_syscfg1_s

syscfg1

)

Writes the syscfg1 struct to the syscfg1 register.

Parameters

[in]

syscfg1

System config 1 register that holds value to be written.

Returns

np0_status_e Status

np0_write_SYSCFG2()

np0_status_e np0_write_SYSCFG2

(

const np0_register_syscfg2_s

syscfg2

)

Writes the syscfg2 struct to the syscfg2 register.

Parameters

[in]

syscfg2

System config 2 register that holds value to be written.

Returns

np0_status_e Status

np0_write_SYSCFG3()

np0_status_e np0_write_SYSCFG3

(

const np0_register_syscfg3_s

syscfg3

)

Writes the syscfg3 struct to the syscfg2 register.

Parameters

[in]

syscfg3

System config 3 register that holds value to be written.

Returns

np0_status_e Status

np0_write_TCFGP()

np0_status_e np0_write_TCFGP	(	const np0_psw_e	sw,
		const np0_register_tcfgp_s	tcfgp )

Writes the tcfgp struct to the tcfgp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	tcfgp	Time To Wait Config Peripheral register that holds the value to be written.

Returns

np0_status_e Status

np0_write_THROVA1()

np0_status_e np0_write_THROVA1

(

const np0_register_throva1_s

throva1

)

Writes the throva1 struct to the throva1 register.

Parameters

[in]

throva1

Threshold Over ADC 1 register that holds value to be written.

Returns

np0_status_e Status

np0_write_THROVA2()

np0_status_e np0_write_THROVA2

(

const np0_register_throva2_s

throva2

)

Writes the throva2 struct to the throva2 register.

Parameters

[in]

throva2

Threshold Over ADC 2 register that holds value to be written.

Returns

np0_status_e Status

np0_write_THROVP()

np0_status_e np0_write_THROVP	(	const np0_psw_e	sw,
		const np0_register_throvp_s	throvp )

Writes the throvp struct to the throvp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	throvp	Threshold Over Peripheral register that holds the value to be written.

Returns

np0_status_e Status

np0_write_THRUNA1()

np0_status_e np0_write_THRUNA1

(

const np0_register_thruna1_s

thruna1

)

Writes the thruna1 struct to the TRHUNA1 register.

Parameters

[in]

thruna1

Threshold Under ADC 1 register that holds value to be written.

Returns

np0_status_e Status

np0_write_THRUNA2()

np0_status_e np0_write_THRUNA2

(

const np0_register_thruna2_s

thruna2

)

Writes the thruna2 struct to the TRHUNA2 register.

Parameters

[out]

thruna2

Threshold Under ADC 2 register that holds value to be written.

Returns

np0_status_e Status

np0_write_THRUNP()

np0_status_e np0_write_THRUNP	(	const np0_psw_e	sw,
		const np0_register_thrunp_s	thrunp )

Writes the thrunp struct to the thrunp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	thrunp	Threshold Under Peripheral register that holds the value to be written.

Returns

np0_status_e Status

np0_write_TOUT()

np0_status_e np0_write_TOUT

(

const np0_register_tout_s

tout

)

Writes the tout struct to the TOUT_L and TOUT_H registers.

Parameters

[in]

tout

Global Timeout register that holds value to be written.

Returns

np0_status_e Status

np0_write_TWTP()

np0_status_e np0_write_TWTP	(	const np0_psw_e	sw,
		const np0_register_twtp_s	twtp )

Writes the twtp struct to the twtp register that is connected to the low power switch.

Parameters

[in]	sw	Low power switch indicates which peripheral that will be written.
[in]	twtp	Time To Wait Peripheral register that holds the value to be written.

Returns

np0_status_e Status