Data Structures

All structs are defined in Inc/npz.h unless otherwise noted.

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Configuration Structs

npz_device_config_s

Top-level device configuration. Pass a pointer to npz_device_configure().

typedef struct {
    // Power Switch Control (PSWCTL)
    uint8_t power_switch_normal_mode_per1 : 1;
    uint8_t power_switch_normal_mode_per2 : 1;
    uint8_t power_switch_normal_mode_per3 : 1;
    uint8_t power_switch_normal_mode_per4 : 1;
    npz_host_power_mode_e host_power_mode;

    // System Config 1 (SYSCFG1) — wake-up sources
    uint8_t wake_up_per1 : 1;
    uint8_t wake_up_per2 : 1;
    uint8_t wake_up_per3 : 1;
    uint8_t wake_up_per4 : 1;
    npz_wakeup_e wake_up_any_or_all : 1;

    // System Config 2 (SYSCFG2) — clock
    npz_sclk_div_e system_clock_divider;
    npz_sclk_sel_e system_clock_source;

    // System Config 3 (SYSCFG3) — pins
    npz_io_str_e        io_strength;
    npz_i2c_pull_sel_e  i2c_pull_mode;
    npz_spi_auto_e      spi_auto;
    npz_xo_clkout_div_e xo_clock_out_sel;

    // Global timeout (TOUT) — 16-bit system clock periods
    uint16_t global_timeout;

    // Interrupt pin pull-ups (INTCFG)
    npz_int_pin_pull_e interrupt_pin_pull_up_pin1;
    npz_int_pin_pull_e interrupt_pin_pull_up_pin2;
    npz_int_pin_pull_e interrupt_pin_pull_up_pin3;
    npz_int_pin_pull_e interrupt_pin_pull_up_pin4;

    // Peripheral configurations (NULL = disabled)
    npz_peripheral_config_s *peripherals[4];

    // ADC (SYSCFG2)
    uint8_t adc_ext_sampling_enable : 1;
    npz_adc_clk_e adc_clock_sel;
    npz_adc_config_channels_s *adc_channels[2]; // [0]=internal, [1]=external
} npz_device_config_s;

Field	Type	Description
power_switch_normal_mode_perN	uint8_t : 1	Normal-mode power switch state for peripheral N (0/1).
host_power_mode	npz_host_power_mode_e	SW_HP pin behaviour (power switch or logic output).
wake_up_perN	uint8_t : 1	Allow peripheral N to wake the host.
wake_up_any_or_all	npz_wakeup_e	Wake on any trigger (WAKEUP_ANY) or require all to fire (WAKEUP_ALL).
system_clock_divider	npz_sclk_div_e	System clock divider.
system_clock_source	npz_sclk_sel_e	10 Hz internal oscillator or 16 Hz clock generated by the 32 kHz crystal.
io_strength	npz_io_str_e	I/O output strength (normal / high).
i2c_pull_mode	npz_i2c_pull_sel_e	Internal I2C pull-up control.
spi_auto	npz_spi_auto_e	SPI pin hi-Z in sleep.
xo_clock_out_sel	npz_xo_clkout_div_e	CLK_OUT frequency (off, 32 kHz … 1 kHz).
global_timeout	uint16_t	System clock periods before unconditional host wake. Must be > 0.
interrupt_pin_pull_up_pinN	npz_int_pin_pull_e	Pull-up strength for INT pin N.
peripherals[4]	npz_peripheral_config_s*	Array of peripheral configs; set to NULL to disable.
adc_ext_sampling_enable	uint8_t : 1	Enable external ADC_IN pin sampling (halves ADC rate when enabled).
adc_clock_sel	npz_adc_clk_e	ADC sampling frequency.
adc_channels[2]	npz_adc_config_channels_s*	[0] = internal (VBAT), [1] = external (ADC_IN). Both must be non-NULL.

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npz_peripheral_config_s

Configuration for one peripheral slot (I²C or SPI).

typedef struct {
    npz_com_protocol_e communication_protocol;
    npz_power_mode_e power_mode;
    npz_polling_mode_e polling_mode;
    npz_power_switch_mode_e power_switch_mode;
    npz_interrupt_pin_mode_e interrupt_pin_mode;
    npz_comparison_mode_e comparison_mode;
    npz_data_type_e sensor_data_type;
    npz_multibyte_e multi_byte_transfer_enable : 1;
    npz_endianess_e swap_registers : 1;
    uint16_t polling_period;        // NOTE: zero is invalid

    union {
        struct {                    // I²C
            uint8_t command_num;
            uint8_t sensor_address;
            uint8_t reg_address_value;
            uint8_t wake_on_nak : 1;
            uint8_t num_of_retries_on_nak : 2;
            uint8_t bytes_from_sram[40];
        } i2c_cfg;
        struct {                    // SPI
            uint8_t bytes_from_sram_num;
            uint8_t bytes_from_sram_read_num;
            uint8_t bytes_from_sram[40];
            uint8_t bytes_from_sram_read[40];
            npz_spimod_e mode;
        } spi_cfg;
    };

    uint16_t threshold_over;
    uint16_t threshold_under;
    uint8_t  time_to_wait;
    npz_pre_wait_time_e  pre_wait_time;
    npz_post_wait_time_e post_wait_time;
} npz_peripheral_config_s;

Field	Type	Description
communication_protocol	npz_com_protocol_e	COM_I2C or COM_SPI. Selects which union member applies.
power_mode	npz_power_mode_e	Disabled, periodic, or always-on.
polling_mode	npz_polling_mode_e	How the IC polls: periodic read/compare, wait-for-interrupt, or async.
power_switch_mode	npz_power_switch_mode_e	SW_LP pin behavior.
interrupt_pin_mode	npz_interrupt_pin_mode_e	INT pin as input (active high/low) or trigger output.
comparison_mode	npz_comparison_mode_e	Inside or outside threshold triggers wake.
sensor_data_type	npz_data_type_e	uint16, int16, or uint8.
multi_byte_transfer_enable	npz_multibyte_e : 1	Send address + value as a single multi-byte I2C write.
swap_registers	npz_endianess_e : 1	Swap high/low bytes for big-endian sensors.
polling_period	uint16_t	Period in system clock periods. Never set to 0.
i2c_cfg.command_num	uint8_t	Number of {reg, value} pairs to send from SRAM for init.
i2c_cfg.sensor_address	uint8_t	7-bit I2C address of the sensor.
i2c_cfg.reg_address_value	uint8_t	Register on the sensor that holds the measurement value.
i2c_cfg.wake_on_nak	uint8_t : 1	Wake host if sensor NAKs its address.
i2c_cfg.num_of_retries_on_nak	uint8_t : 2	Retry count on NAK (0 = no retries).
i2c_cfg.bytes_from_sram[40]	uint8_t[]	Flat byte array: {reg0, val0, reg1, val1, …} for init.
spi_cfg.bytes_from_sram_num	uint8_t	Total bytes to send from SRAM during init.
spi_cfg.bytes_from_sram_read_num	uint8_t	Bytes from SRAM to use as the SPI read command.
spi_cfg.bytes_from_sram[40]	uint8_t[]	Bytes for SPI init sequence.
spi_cfg.bytes_from_sram_read[40]	uint8_t[]	Bytes for SPI read command.
spi_cfg.mode	npz_spimod_e	SPI mode (CPOL/CPHA).
threshold_over	uint16_t	Upper threshold (must match sensor_data_type).
threshold_under	uint16_t	Lower threshold.
time_to_wait	uint8_t	Wait units (x256 or x4096 of internal 400 kHz clock).
pre_wait_time	npz_pre_wait_time_e	Apply wait before init sequence, after peripheral power up
post_wait_time	npz_post_wait_time_e	Apply wait after init sequence, before peripheral read

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npz_adc_config_channels_s

Configuration for one ADC channel.

typedef struct {
    uint8_t over_threshold;    // 5-bit unsigned
    uint8_t under_threshold;   // 5-bit unsigned
    uint8_t wakeup_enable : 1;
} npz_adc_config_channels_s;

Field	Type	Description
over_threshold	uint8_t	5-bit/6-bit code — reading at or above this value triggers wake-up (if enabled).
under_threshold	uint8_t	5-bit/6-bit code — reading at or below this value triggers wake-up (if enabled).
wakeup_enable	uint8_t : 1	1 = this ADC channel can wake the host.

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Register Structs

These map directly to IC hardware registers. Used with the low-level npz_read_* / npz_write_* functions.

npz_register_sta1_s

typedef struct {
    npz_resetsource_e reset_source : 3;
    uint8_t padding : 2;
    uint8_t ext_adc_triggered : 1;
    uint8_t int_adc_triggered : 1;
    uint8_t global_timeout_triggered : 1;
} npz_register_sta1_s;

Field	Description
reset_source	Last reset cause — power-on, external (RST pin), or soft reset.
ext_adc_triggered	External ADC (ADC_IN) threshold crossed.
int_adc_triggered	Internal ADC (VBAT) threshold crossed.
global_timeout_triggered	Global timeout expired before any other wake-up source triggered.

---

npz_register_sta2_s

typedef struct {
    uint8_t per1_triggered : 1;
    uint8_t per1_global_timeout : 1;
    uint8_t per2_triggered : 1;
    uint8_t per2_global_timeout : 1;
    uint8_t per3_triggered : 1;
    uint8_t per3_global_timeout : 1;
    uint8_t per4_triggered : 1;
    uint8_t per4_global_timeout : 1;
} npz_register_sta2_s;

Each peripheral has a _triggered bit (threshold crossed) and a _global_timeout bit (IC timed out waiting for that peripheral).

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npz_register_pswctl_s

typedef struct {
    uint8_t pswint_p1 : 1;
    uint8_t pswint_p2 : 1;
    uint8_t pswint_p3 : 1;
    uint8_t pswint_p4 : 1;
    npz_host_power_mode_e pswh_mode : 2;
    uint8_t psw_en_vn : 1;
    uint8_t psw_vn_on : 1;
} npz_register_pswctl_s;

Field	Description
pswint_pN	Controls power switch output state for peripheral N.
pswh_mode	Host SW_HP pin mode — power switch or logic output.
psw_en_vn	Gate boost enable for reduced Rds(on). NOTE: Not functional in the nPZero G1S!
psw_vn_on	Read-only: 1 when gate boost is active.

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npz_register_cfgp_s

typedef struct {
    npz_power_mode_e        pwmod  : 2;
    npz_polling_mode_e      tmod   : 2;
    npz_power_switch_mode_e pswmod : 2;
    npz_interrupt_pin_mode_e intmod : 2;
} npz_register_cfgp_s;

---

npz_register_modp_s

typedef struct {
    npz_comparison_mode_e cmod   : 1;
    npz_data_type_e       dtype  : 2;
    uint8_t               seqrw  : 1;
    uint8_t               wunak  : 1;
    uint8_t               swprreg : 1;
    npz_spimod_e          spimod : 2;
} npz_register_modp_s;

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Other Register Structs

Struct	Register	Key Fields
npz_register_idle_rst_s	IDLE_RST	value (0xFF = enter idle, 0xA5 = soft reset)
npz_register_id_s	ID	id (read-only chip ID)
npz_register_syscfg1_s	SYSCFG1	wup1–wup4, ADC wake enables, wake_up_any_or_all
npz_register_syscfg2_s	SYSCFG2	sclk_div_en, sclk_div_sel, sclk_sel, adc_ext_on, adc_clk_sel
npz_register_syscfg3_s	SYSCFG3	io_str, i2c_pup_en, i2c_pup_auto, spi_auto, xo_clkout_div
npz_register_tout_s	TOUT_L/H	tout_l, tout_h (16-bit timeout)
npz_register_intcfg_s	INTCFG	pu_intN, pu_s_intN for N=1-4
npz_register_perp_s	PERP_L/H	perp_l, perp_h (16-bit polling period)
npz_register_ncmdp_s	NCMDP	ncmdp (7-bit command count)
npz_register_addrp_s	ADDRP	addrp (7-bit I2C addr / SPI byte count), spi_en
npz_register_rregp_s	RREGP	rregp (sensor data register address)
npz_register_throvp_s	THROVP_L/H	throvp_l, throvp_h
npz_register_thrunp_s	THRUNP_L/H	thrunp_l, thrunp_h
npz_register_twtp_s	TWTP	twtp (wait time units)
npz_register_tcfgp_s	TCFGP	twt_en, twt_ext, tinit_en, tinit_ext, i2cret
npz_register_throva1_s	THROVA1	throva (5-bit internal ADC over threshold)
npz_register_thruna1_s	THRUNA1	thruna (5-bit internal ADC under threshold)
npz_register_throva2_s	THROVA2	throva (6-bit external ADC over threshold)
npz_register_thruna2_s	THRUNA2	thruna (6-bit external ADC under threshold)
npz_register_valp_s	VALP_L/H	valp_l, valp_h (last read peripheral value)
npz_register_adc_core_s	ADC_CORE	adc_core (5-bit VBAT ADC code)
npz_register_adc_ext_s	ADC_EXT	adc_ext (6-bit ADC_IN code)
npz_register_sram_s	SRAM	value[128]
npz_status_s	STA1/2	status1 (STA1), status2 (STA2)