Enumerations
All enumerations are defined in Inc/npz.h unless noted. HAL status codes are defined in Inc/npz_hal.h.
HAL Status
npz_status_e
File: npz_hal.h
Return type for all HAL and register-access functions.
| Enumerator | Value | Description |
|---|---|---|
OK | 0x00 | Operation completed successfully. |
ERR | 0x01 | I2C transaction or peripheral error. |
INVALID_PARAM | 0x02 | A parameter was invalid or out of range. |
System / Device
npz_resetsource_e
Source of the last device reset, read from npz_register_sta1_s.reset_source.
| Enumerator | Value | Description |
|---|---|---|
RESETSOURCE_NONE | 0x00 | No reset. |
RESETSOURCE_PWR_RESET | 0x01 | Power-on reset. |
RESETSOURCE_EXT_RESET | 0x02 | External reset via RST pin. |
RESETSOURCE_SOFT_RESET | 0x04 | Software reset via I²C command (0xA5). |
npz_host_power_mode_e
Behavior of the SW_HP host power switch pin.
| Enumerator | Value | Description |
|---|---|---|
HOST_POWER_MODE_SWITCH | 0x01 | Power switch: outputs VBAT when host is enabled, open otherwise. |
HOST_POWER_MODE_LOGIC_OUTPUT | 0x02 | Logic output: high when host is enabled. |
HOST_POWER_MODE_LOGIC_OUTPUT_INV | 0x03 | Logic output inverted: low when host is enabled. |
npz_psw_e
Selects a peripheral slot (low-power switch). Used in all peripheral register functions.
| Enumerator | Value | Description |
|---|---|---|
PSW_LP1 | 0x01 | Peripheral 1. |
PSW_LP2 | 0x02 | Peripheral 2. |
PSW_LP3 | 0x03 | Peripheral 3. |
PSW_LP4 | 0x04 | Peripheral 4. |
npz_wakeup_e
Controls whether any single trigger or all triggers must fire to wake the host.
| Enumerator | Value | Description |
|---|---|---|
WAKEUP_ANY | 0x00 | Wake on any enabled trigger. |
WAKEUP_ALL | 0x01 | Require all enabled triggers to fire before waking. |
npz_states_e
Generic enabled/disabled state.
| Enumerator | Value |
|---|---|
DISABLED | 0x00 |
ENABLED | 0x01 |
Clock
npz_sclk_sel_e
System clock source.
| Enumerator | Value | Description |
|---|---|---|
SYS_CLOCK_10HZ | 0x00 | Internal slow oscillator (~10 Hz). |
SYS_CLOCK_32KHZ | 0x01 | Crystal oscillator (~16 Hz generated from 32.768 kHz source). |
npz_sclk_div_e
System clock divider.
| Enumerator | Value | Description |
|---|---|---|
SCLK_DIV_DISABLE | 0x00 | No division. |
SCLK_DIV_2 | 0x01 | Divide by 2. |
SCLK_DIV_4 | 0x03 | Divide by 4. |
SCLK_DIV_8 | 0x05 | Divide by 8. |
SCLK_DIV_16 | 0x07 | Divide by 16. |
npz_adc_clk_e
ADC sampling frequency.
| Enumerator | Value | Description |
|---|---|---|
ADC_CLK_SC | 0x00 | System clock (default). |
ADC_CLK_64 | 0x01 | XO ÷ 512 = 64 Hz. |
ADC_CLK_256 | 0x02 | XO ÷ 128 = 256 Hz. |
ADC_CLK_1024 | 0x03 | XO ÷ 32 = 1024 Hz. |
XO-derived ADC clocks (ADC_CLK_64, ADC_CLK_256, ADC_CLK_1024) require system_clock_source = SYS_CLOCK_32KHZ.
npz_xo_clkout_div_e
CLK_OUT pin frequency (crystal oscillator output).
| Enumerator | Value | Frequency |
|---|---|---|
XO_CLK_OFF | 0x00 | Disabled. |
XO_CLK_32K | 0x01 | 32 kHz (÷1). |
XO_CLK_16K | 0x02 | 16 kHz (÷2). |
XO_CLK_8K | 0x03 | 8 kHz (÷4). |
XO_CLK_4K | 0x04 | 4 kHz (÷8). |
XO_CLK_2K | 0x05 | 2 kHz (÷16). |
XO_CLK_1K | 0x06 | 1 kHz (÷32). |
Peripheral Configuration
npz_power_mode_e
Peripheral power supply mode.
| Enumerator | Value | Description |
|---|---|---|
POWER_MODE_DISABLED | 0x00 | Peripheral power off; slot unused. |
POWER_MODE_PERIODIC | 0x01 | Power on periodically for each poll cycle. |
POWER_MODE_ALWAYS_ON | 0x03 | Power permanently on. |
npz_polling_mode_e
How the nPZero interacts with the peripheral each cycle.
| Enumerator | Value | Description |
|---|---|---|
POLLING_MODE_PERIODIC_READ_COMPARE_THRESHOLD | 0x00 | Init → read → compare against threshold. |
POLLING_MODE_PERIODIC_WAIT_INTERRUPT_COMPARE_THRESHOLD | 0x01 | Init → wait for INT → read → compare. |
POLLING_MODE_PERIODIC_WAIT_INTERRUPT | 0x02 | Init → wait for INT (no data read or compare). |
POLLING_MODE_ASYNC_WAIT_INTERRUPT | 0x03 | Wait for asynchronous interrupt only. |
npz_power_switch_mode_e
Behavior of the SW_LP peripheral power switch pin.
| Enumerator | Value | Description |
|---|---|---|
POWER_SWITCH_MODE_STANDARD | 0x01 | Standard power switch. |
POWER_SWITCH_MODE_LOGIC_OUTPUT_HIGH | 0x02 | Logic output: high when peripheral enabled. |
POWER_SWITCH_MODE_LOGIC_OUTPUT_LOW | 0x03 | Logic output inverted: low when peripheral enabled. |
npz_interrupt_pin_mode_e
Mode of the INT interrupt pin for the peripheral.
| Enumerator | Value | Description |
|---|---|---|
INTERRUPT_PIN_MODE_INPUT_ACTIVE_HIGH | 0x00 | Input — asserted high by the peripheral. |
INTERRUPT_PIN_MODE_INPUT_ACTIVE_LOW | 0x01 | Input — asserted low by the peripheral. |
INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_HIGH | 0x02 | Output — Active high trigger. |
INTERRUPT_PIN_MODE_TRIGGER_OUTPUT_LOW | 0x03 | Output — Active low trigger. |
npz_comparison_mode_e
How over/under thresholds define the trigger condition.
| Enumerator | Value | Description |
|---|---|---|
COMPARISON_MODE_INSIDE_THRESHOLD | 0x00 | Triggers when value ≥ over threshold OR ≤ under threshold. |
COMPARISON_MODE_OUTSIDE_THRESHOLD | 0x01 | Triggers when value < over threshold AND > under threshold. |
npz_data_type_e
Data type of the value read from the peripheral.
| Enumerator | Value | Description |
|---|---|---|
DATA_TYPE_UINT16 | 0x00 | 16-bit unsigned integer. |
DATA_TYPE_INT16 | 0x01 | 16-bit signed integer. |
DATA_TYPE_UINT8 | 0x02 | 8-bit unsigned integer. |
npz_com_protocol_e
Communication protocol for the peripheral.
| Enumerator | Value | Description |
|---|---|---|
COM_I2C | 0x00 | I2C — use i2c_cfg union member. |
COM_SPI | 0x01 | SPI — use spi_cfg union member. |
npz_endianess_e
Byte order of the 16-bit value read from the peripheral.
| Enumerator | Value | Description |
|---|---|---|
ENDIAN_LITTLE | 0x00 | Low byte at RREGP, high byte at RREGP+1. |
ENDIAN_BIG | 0x01 | High byte at RREGP, low byte at RREGP+1. |
npz_multibyte_e
Multi-byte I2C transfer mode.
| Enumerator | Value | Description |
|---|---|---|
MULTIBYTE_TRANSFER_DISABLE | 0x00 | Each init command sent as separate I2C transaction. |
MULTIBYTE_TRANSFER_ENABLE | 0x01 | Sequential register addresses sent as a single multi-byte write. |
npz_spimod_e
SPI clock polarity and phase.
| Enumerator | Value | CPOL | CPHA |
|---|---|---|---|
SPIMOD_SPI_MODE_0 | 0x00 | 0 | 0 |
SPIMOD_SPI_MODE_1 | 0x01 | 0 | 1 |
SPIMOD_SPI_MODE_2 | 0x02 | 1 | 0 |
SPIMOD_SPI_MODE_3 | 0x03 | 1 | 1 |
Wait Time
npz_pre_wait_time_e
Wait time inserted before peripheral initialization sequence.
| Enumerator | Value | Duration |
|---|---|---|
PRE_WAIT_TIME_DISABLED | 0x00 | No pre-init wait. |
PRE_WAIT_TIME_EXTEND_256 | 0x01 | TWTP x 256 periods of internal 400 kHz clock. |
PRE_WAIT_TIME_EXTEND_4096 | 0x03 | TWTP x 4096 periods of internal 400 kHz clock. |
npz_post_wait_time_e
Wait time inserted after peripheral initialization sequence.
| Enumerator | Value | Duration |
|---|---|---|
POST_WAIT_TIME_DISABLED | 0x00 | No post-init wait. |
POST_WAIT_TIME_EXTEND_256 | 0x01 | TWTP x 256 periods of internal 400 kHz clock. |
POST_WAIT_TIME_EXTEND_4096 | 0x03 | TWTP x 4096 periods of internal 400 kHz clock. |
I/O Pin Configuration
npz_io_str_e
I/O output strength.
| Enumerator | Value | Description |
|---|---|---|
IO_STR_NORMAL | 0x00 | Normal push/pull strength. |
IO_STR_HIGH | 0x01 | High push/pull strength. |
npz_i2c_pull_sel_e
Internal I2C pull-up resistor (~40 kΩ) control.
| Enumerator | Value | Description |
|---|---|---|
I2C_PULL_DISABLE | 0x00 | Pull-ups always disabled. |
I2C_PULL_ALWAYS_ON | 0x01 | Pull-ups always enabled. |
I2C_PULL_AUTO | 0x03 | Pull-ups enabled in active mode, disabled in idle. |
npz_spi_auto_e
SPI pin state when the interface is idle.
| Enumerator | Value | Description |
|---|---|---|
SPI_PINS_ALWAYS_ON | 0x00 | SPI pins always driven. |
SPI_PINS_AUTO_DISABLE | 0x01 | SPI pins high-Z when interface is not in use (idle). |
npz_int_pin_pull_e
Internal pull-up configuration for INT interrupt input pins.
| Enumerator | Value | Description |
|---|---|---|
INT_PIN_PULL_DISABLED | 0x00 | No internal pull-up. |
INT_PIN_PULL_LOW | 0x01 | Low-strength pull-up enabled. |
INT_PIN_PULL_HIGH | 0x03 | High-strength pull-up enabled. |