Register Map

All register addresses are defined in Inc/npz_registers.h. For a complete description of the nPZero registers, please refer to the datasheet available at the documentation page

System Registers

Address	Macro	Name	Access	Description
`0x00`	`REG_IDLE_RST`	Idle/Reset	R/W	Write `0xFF` = idle, `0xA5` = soft reset.
`0x01`	`REG_ID`	Chip ID	R	Device identification byte.
`0x02`	`REG_STA1`	Status 1	R	Reset source, ADC triggers, global timeout flag.
`0x03`	`REG_STA2`	Status 2	R	Peripheral triggered or peripheral NAK flags.
`0x04`	`REG_PSWCTL`	Power Switch Control	R/W	Host and peripheral switch modes.
`0x05`	`REG_SYSCFG1`	System Config 1	R/W	Wake-up source enables and any/all logic.
`0x06`	`REG_SYSCFG2`	System Config 2	R/W	Clock source, divider, ADC clock and ext ADC enable.
`0x07`	`REG_SYSCFG3`	System Config 3	R/W	I/O strength, I²C pull-ups, SPI auto, CLK_OUT.
`0x08`	`REG_TOUT_L`	Global Timeout Low	R/W	Lower 8 bits of 16-bit timeout.
`0x09`	`REG_TOUT_H`	Global Timeout High	R/W	Upper 8 bits of 16-bit timeout.
`0x0A`	`REG_INTCFG`	Interrupt Pin Config	R/W	INT1-INT4 pull-up enable and strength.

Peripheral 1 Registers

Address	Macro	Name	Description
`0x10`	`REG_CFGP1`	Config P1	Power mode, polling mode, switch mode, INT mode.
`0x11`	`REG_MODP1`	Mode P1	Comparison mode, data type, multi-byte, endian, SPI mode, NAK wake.
`0x12`	`REG_PERP1_L`	Polling Period P1 Low	Lower 8 bits of 16-bit polling period.
`0x13`	`REG_PERP1_H`	Polling Period P1 High	Upper 8 bits of 16-bit polling period.
`0x14`	`REG_NCMDP1`	Num Commands P1	7-bit init command count (I²C) or byte count (SPI).
`0x15`	`REG_ADDRP1`	Address P1	I²C: 7-bit sensor address + SPI enable flag.
`0x16`	`REG_RREGP1`	Read Register P1	I²C sensor register holding measurement data.
`0x17`	`REG_THROVP1_L`	Over Threshold P1 Low	Lower byte of 16-bit over threshold.
`0x18`	`REG_THROVP1_H`	Over Threshold P1 High	Upper byte of 16-bit over threshold.
`0x19`	`REG_THRUNP1_L`	Under Threshold P1 Low	Lower byte of 16-bit under threshold.
`0x1A`	`REG_THRUNP1_H`	Under Threshold P1 High	Upper byte of 16-bit under threshold.
`0x1B`	`REG_TWTP1`	Time to Wait P1	Pre/post-init wait duration in TWTP units.
`0x1C`	`REG_TCFGP1`	Time to Wait Config P1	Wait enable/extend bits and NAK retry count.

Peripheral 2 Registers

Address	Macro	Name	Description
`0x1D`	`REG_CFGP2`	Config P2	Same fields as P1.
`0x1E`	`REG_MODP2`	Mode P2
`0x1F`	`REG_PERP2_L`	Polling Period P2 Low
`0x20`	`REG_PERP2_H`	Polling Period P2 High
`0x21`	`REG_NCMDP2`	Num Commands P2
`0x22`	`REG_ADDRP2`	Address P2
`0x23`	`REG_RREGP2`	Read Register P2
`0x24`	`REG_THROVP2_L`	Over Threshold P2 Low
`0x25`	`REG_THROVP2_H`	Over Threshold P2 High
`0x26`	`REG_THRUNP2_L`	Under Threshold P2 Low
`0x27`	`REG_THRUNP2_H`	Under Threshold P2 High
`0x28`	`REG_TWTP2`	Time to Wait P2
`0x29`	`REG_TCFGP2`	Time to Wait Config P2

Peripheral 3 Registers

Address	Macro	Name	Description
`0x2A`	`REG_CFGP3`	Config P3	Same fields as P1.
`0x2B`	`REG_MODP3`	Mode P3
`0x2C`	`REG_PERP3_L`	Polling Period P3 Low
`0x2D`	`REG_PERP3_H`	Polling Period P3 High
`0x2E`	`REG_NCMDP3`	Num Commands P3
`0x2F`	`REG_ADDRP3`	Address P3
`0x30`	`REG_RREGP3`	Read Register P3
`0x31`	`REG_THROVP3_L`	Over Threshold P3 Low
`0x32`	`REG_THROVP3_H`	Over Threshold P3 High
`0x33`	`REG_THRUNP3_L`	Under Threshold P3 Low
`0x34`	`REG_THRUNP3_H`	Under Threshold P3 High
`0x35`	`REG_TWTP3`	Time to Wait P3
`0x36`	`REG_TCFGP3`	Time to Wait Config P3

Peripheral 4 Registers

Address	Macro	Name	Description
`0x37`	`REG_CFGP4`	Config P4	Same fields as P1.
`0x38`	`REG_MODP4`	Mode P4
`0x39`	`REG_PERP4_L`	Polling Period P4 Low
`0x3A`	`REG_PERP4_H`	Polling Period P4 High
`0x3B`	`REG_NCMDP4`	Num Commands P4
`0x3C`	`REG_ADDRP4`	Address P4
`0x3D`	`REG_RREGP4`	Read Register P4
`0x3E`	`REG_THROVP4_L`	Over Threshold P4 Low
`0x3F`	`REG_THROVP4_H`	Over Threshold P4 High
`0x40`	`REG_THRUNP4_L`	Under Threshold P4 Low
`0x41`	`REG_THRUNP4_H`	Under Threshold P4 High
`0x42`	`REG_TWTP4`	Time to Wait P4
`0x43`	`REG_TCFGP4`	Time to Wait Config P4

ADC Threshold Registers

Address	Macro	Name	Description
`0x44`	`REG_THROVA1`	Over Threshold Internal ADC	5-bit VBAT over threshold code.
`0x45`	`REG_THRUNA1`	Under Threshold Internal ADC	5-bit VBAT under threshold code.
`0x46`	`REG_THROVA2`	Over Threshold External ADC	6-bit ADC_IN over threshold code.
`0x47`	`REG_THRUNA2`	Under Threshold External ADC	6-bit ADC_IN under threshold code.

Value Registers (Read-only)

Address	Macro	Name	Description
`0x50`	`REG_VALP1_L`	Value P1 Low	Last measurement low byte (P1).
`0x51`	`REG_VALP1_H`	Value P1 High	Last measurement high byte (P1).
`0x52`	`REG_VALP2_L`	Value P2 Low
`0x53`	`REG_VALP2_H`	Value P2 High
`0x54`	`REG_VALP3_L`	Value P3 Low
`0x55`	`REG_VALP3_H`	Value P3 High
`0x56`	`REG_VALP4_L`	Value P4 Low
`0x57`	`REG_VALP4_H`	Value P4 High
`0x58`	`REG_ADC_CORE`	Internal ADC Value	Last VBAT 5-bit code.
`0x59`	`REG_ADC_EXT`	External ADC Value	Last ADC_IN 6-bit code.

SRAM

Address	Macro	Description
`0x80`	`REG_SRAM_START`	First SRAM byte. Used to store peripheral init sequences.
`0xFF`	`REG_SRAM_END`	Last SRAM byte.
—	`SRAM_REG_SIZE` (`0x80`)	128 bytes SRAM available.

Total SRAM size: 128 bytes (0x80-0xFF). The driver allocates SRAM sequentially across all configured peripherals at configuration time.

System Registers​

Peripheral 1 Registers​

Peripheral 2 Registers​

Peripheral 3 Registers​

Peripheral 4 Registers​

ADC Threshold Registers​

Value Registers (Read-only)​

SRAM​