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Register Access API — npz.h / npz.c

Low-level read and write functions for every nPZero IC register. These are used internally by the device control layer; use them directly only when you need fine-grained register control.

All functions return npz_status_e: OK (0), ERR (1), or INVALID_PARAM (2).

Generic Register Read​

npz_status_e npz_read_register(uint8_t register_address, void *buffer, size_t size);

Reads size bytes from register_address into buffer using the HAL. All typed npz_read_* functions call this function internally.

System Registers​

Idle / Reset​

npz_status_e npz_write_IDLE_RST(uint8_t idle_rst_value);
npz_status_e npz_read_IDLE_RST(uint8_t *idle_rst_value);
Write ValueEffect
0xFFEnter idle mode — host power off, the nPZero takes control over the I2C bus.
0xA5Software reset — returns to power-on defaults.

Chip ID​

npz_status_e npz_read_ID(uint8_t *id);

Reads the device identification register. Useful for verifying I2C connectivity at startup.

Status Registers (Read-only)​

npz_status_e npz_read_STA1(npz_register_sta1_s *sta1);
npz_status_e npz_read_STA2(npz_register_sta2_s *sta2);

Read after wake-up to determine the trigger source. See npz_register_sta1_s and npz_register_sta2_s.

Power Switch Control​

npz_status_e npz_write_PSWCTL(const npz_register_pswctl_s pswctl);
npz_status_e npz_read_PSWCTL(npz_register_pswctl_s *pswctl);

Controls host and peripheral power switch output states and gate boost. See npz_register_pswctl_s.

System Config 1 (Wake Sources)​

npz_status_e npz_write_SYSCFG1(const npz_register_syscfg1_s syscfg1);
npz_status_e npz_read_SYSCFG1(npz_register_syscfg1_s *syscfg1);

Enables peripheral and ADC wake-up sources, and selects any-vs-all wake logic.

System Config 2 (Clock & ADC)​

npz_status_e npz_write_SYSCFG2(const npz_register_syscfg2_s syscfg2);
npz_status_e npz_read_SYSCFG2(npz_register_syscfg2_s *syscfg2);

Configures system clock source, divider, external ADC enable, and ADC clock.

System Config 3 (Pin / I²C / SPI / CLK_OUT)​

npz_status_e npz_write_SYSCFG3(const npz_register_syscfg3_s syscfg3);
npz_status_e npz_read_SYSCFG3(npz_register_syscfg3_s *syscfg3);

Configures I/O strength, I2C pull-ups, SPI auto-disable, and CLK_OUT divider.

Global Timeout​

npz_status_e npz_write_TOUT(const npz_register_tout_s tout);
npz_status_e npz_read_TOUT(npz_register_tout_s *tout);

Sets/reads the 16-bit timeout value (system clock periods) before the host is unconditionally woken.

Interrupt Pin Config​

npz_status_e npz_write_INTCFG(const npz_register_intcfg_s intcfg);
npz_status_e npz_read_INTCFG(npz_register_intcfg_s *intcfg);

Configures the internal pull-up enable and strength for INT1-INT4 pins.

Peripheral Registers​

All peripheral register functions take a npz_psw_e sw parameter to select the peripheral slot:

sw ValuePeripheral
PSW_LP1Peripheral 1
PSW_LP2Peripheral 2
PSW_LP3Peripheral 3
PSW_LP4Peripheral 4

Config Peripheral (CFGP)​

npz_status_e npz_write_CFGP(const npz_psw_e sw, const npz_register_cfgp_s cfgp);
npz_status_e npz_read_CFGP(const npz_psw_e sw, npz_register_cfgp_s *cfgp);

Power mode, polling mode, power switch mode, interrupt pin mode.

Mode Peripheral (MODP)​

npz_status_e npz_write_MODP(const npz_psw_e sw, const npz_register_modp_s modp);
npz_status_e npz_read_MODP(const npz_psw_e sw, npz_register_modp_s *modp);

Comparison mode, data type, multi-byte transfers, endianness, NAK wake, SPI mode.

Polling Period (PERP)​

npz_status_e npz_write_PERP(const npz_psw_e sw, const npz_register_perp_s perp);
npz_status_e npz_read_PERP(const npz_psw_e sw, npz_register_perp_s *perp);

16-bit polling period in system clock periods. Zero is not valid.

Number of Init Commands (NCMDP)​

npz_status_e npz_write_NCMDP(const npz_psw_e sw, const npz_register_ncmdp_s ncmdp);
npz_status_e npz_read_NCMDP(const npz_psw_e sw, npz_register_ncmdp_s *ncmdp);

I2C: number of address+value command pairs in SRAM. SPI: total bytes to send from SRAM.

Peripheral Address (ADDRP)​

npz_status_e npz_write_ADDRP(const npz_psw_e sw, const npz_register_addrp_s addrp);
npz_status_e npz_read_ADDRP(const npz_psw_e sw, npz_register_addrp_s *addrp);

I2C: 7-bit sensor address. SPI: number of bytes to send from SRAM for the read command. Also selects I2C vs SPI via spi_en.

Read Register Peripheral (RREGP)​

npz_status_e npz_write_RREGP(const npz_psw_e sw, const npz_register_rregp_s rregp);
npz_status_e npz_read_RREGP(const npz_psw_e sw, npz_register_rregp_s *rregp);

I2C only: the register address on the peripheral that contains the value to be read.

Over/Under Threshold Peripheral (THROVP / THRUNP)​

npz_status_e npz_write_THROVP(const npz_psw_e sw, const npz_register_throvp_s throvp);
npz_status_e npz_read_THROVP(const npz_psw_e sw, npz_register_throvp_s *throvp);

npz_status_e npz_write_THRUNP(const npz_psw_e sw, const npz_register_thrunp_s thrunp);
npz_status_e npz_read_THRUNP(const npz_psw_e sw, npz_register_thrunp_s *thrunp);

16-bit over and under threshold values. Must match the data type set in MODP.

Time to Wait / Config (TWTP / TCFGP)​

npz_status_e npz_write_TWTP(const npz_psw_e sw, const npz_register_twtp_s twtp);
npz_status_e npz_read_TWTP(const npz_psw_e sw, npz_register_twtp_s *twtp);

npz_status_e npz_write_TCFGP(const npz_psw_e sw, const npz_register_tcfgp_s tcfgp);
npz_status_e npz_read_TCFGP(const npz_psw_e sw, npz_register_tcfgp_s *tcfgp);

TWTP sets the wait duration (in units of 256 or 4096 × 400 kHz periods). TCFGP controls pre/post-init wait enable, extension, and NAK retry count.

Peripheral Value (VALP — Read-only)​

npz_status_e npz_read_VALP(const npz_psw_e sw, npz_register_valp_s *valp);

Reads the last captured value from the peripheral. Valid only after a threshold trigger.

ADC Registers​

Over/Under Threshold — Internal ADC (THROVA1 / THRUNA1)​

npz_status_e npz_write_THROVA1(const npz_register_throva1_s throva1);
npz_status_e npz_read_THROVA1(npz_register_throva1_s *throva1);

npz_status_e npz_write_THRUNA1(const npz_register_thruna1_s thruna1);
npz_status_e npz_read_THRUNA1(npz_register_thruna1_s *thruna1);

5-bit threshold codes for the internal VBAT ADC channel.

Over/Under Threshold — External ADC (THROVA2 / THRUNA2)​

npz_status_e npz_write_THROVA2(const npz_register_throva2_s throva2);
npz_status_e npz_read_THROVA2(npz_register_throva2_s *throva2);

npz_status_e npz_write_THRUNA2(const npz_register_thruna2_s thruna2);
npz_status_e npz_read_THRUNA2(npz_register_thruna2_s *thruna2);

6-bit threshold codes for the external ADC_IN channel.

ADC Values (Read-only)​

npz_status_e npz_read_ADC_CORE(npz_register_adc_core_s *adc_core);
npz_status_e npz_read_ADC_EXT(npz_register_adc_ext_s *adc_ext);

Read the last sampled 5-bit code from the internal (VBAT) or 6-bit code from the external (ADC_IN) ADC channel.

SRAM​

npz_status_e npz_write_SRAM(const uint8_t sram_reg, const uint8_t sram);
npz_status_e npz_read_SRAM(const uint8_t sram_reg, npz_register_sram_s *sram);

Writes or reads a single byte at address sram_reg within the SRAM range 0x80-0xFF (128 bytes total, SRAM_REG_SIZE = 0x80). The init sequences for peripherals are stored here by npz_device_configure() automatically.

ConstantValueDescription
REG_SRAM_START0x80First SRAM byte address.
REG_SRAM_END0xFFLast SRAM byte address.
SRAM_REG_SIZE0x80128 bytes total SRAM size.